View M93C06-R_311695.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M93C86, M93C76, M93C66 M93C56, M93C46, M93C06
16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM
FEATURES SUMMARY s Industry Standard MICROWIRE Bus
s
Figure 1. Packages
Single Supply Voltage: - 4.5V to 5.5V for M93Cx6 - 2.5V to 5.5V for M93Cx6-W - 1.8V to 5.5V for M93Cx6-R
8 1
PDIP8 (BN)
s s
Dual Organization: by Word (x16) or Byte (x8) Programming Instructions that work on: Byte, Word or Entire Memory Self-timed Programming Cycle with Auto-Erase Ready/Busy Signal During Programming Speed: - 1MHz Clock Rate, 10ms Write Time (Current product, identified by process identification letter F or M) - 2MHz Clock Rate, 5ms Write Time (New Product, identified by process identification letter W)
s s s
8 1
SO8 (MN) 150 mil width
s s s s
Sequential Read Operation Enhanced ESD/Latch-Up Behaviour More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
TSSOP8 (DS) 3x3mm body size
TSSOP8 (DW) 169 mil width
M93C06 IS "NOT FOR NEW DESIGN" The M93C06 is still in production, but is not recommended for new designs. Please refer to AN1571
on how to replace the M93C06 by the M93C46 in your application.
February 2003
1/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed through a Serial Data Input (D) and Serial Data Output (Q) using the MICROWIRE bus protocol. Figure 2. Logic Diagram
Table 2. Memory Size versus Organization
Device Number of Bits 16384 8192 4096 2048 1024 256 Number of 8-bit Bytes 2048 1024 512 256 128 32 Number of 16-bit Words 1024 512 256 128 64 16
M93C86 M93C76 M93C66
VCC
M93C56 M93C46
D C M93Cx6 S ORG
Q
M93C061
Note: 1. Not for New Design
The M93Cx6 is accessed by a set of instructions, as summarized in Table 3, and in more detail in Table 4 to Table 6). Table 3. Instruction Set for the M93Cx6
VSS
AI01928
Instruction READ WRITE EWEN EWDS ERASE
Description Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
Data Byte or Word Byte or Word
Byte or Word
Table 1. Signal Names
S D Q C ORG VCC VSS Chip Select Input
ERAL WRAL
Serial Data Input Serial Data Output Serial Clock Organisation Select Supply Voltage Ground
The memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on Organization Select (ORG). The bit, byte and word sizes of the memories are as shown in Table 2.
A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The address register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cy-
2/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
cle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low. Figure 3. DIP, SO and TSSOP Connections MEMORY ORGANIZATION The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to VSS or VCC for minimum power consumption. Any voltage between VSS and V CC applied to Organization Select (ORG) may increase the stand-by current. The DU (Don't Use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or V SS. Direct connection of DU to VSS is recommended for the lowest stand-by power consumption.
M93Cx6 S C D Q 1 2 3 4 8 7 6 5
AI01929B
VCC DU ORG VSS
Note: 1. See page 21 (onwards) for package dimensions, and how to identify pin-1. 2. DU = Don't Use.
Figure 4. 90 Turned-SO Connections
M93Cx6 DU VCC S C 1 2 3 4 8 7 6 5
AI00900B
ORG VSS Q D
Note: 1. See page 24 for package dimensions, and how to identify pin-1. 2. DU = Don't Use.
POWER-ON DATA PROTECTION To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode. - At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value VCC specified in Table 8 to Table 10. - When VCC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions. For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V.
3/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
INSTRUCTIONS The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 5: s Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low.
s
s
A start bit, which is the first `1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).
The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 6).
s
The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 19 to Table 22.
Table 4. Instruction Set for the M93C46 and M93C06
x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data x16 Origination (ORG = 1) Data Required Clock Cycles Required Clock Address1,3 Cycles A5-A0 18 10 10 10 10 D7-D0 18 A5-A0 11 XXXX 00 XXXX A5-A0 10 XXXX 01 XXXX D15-D0
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A6-A0 A6-A0 11X XXXX 00X XXXX A6-A0 10X XXXX 01X XXXX
Q7-Q0 D7-D0
Q15-Q0 D15-D0 25 9 9 9 9 25
Note: 1. X = Don't Care bit. 2. Address bits A6 and A5 are not decoded by the M93C06. 3. Address bits A5 and A4 are not decoded by the M93C06.
4/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 5. Instruction Set for the M93C56 and M93C66
x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data x16 Origination (ORG = 1) Data Required Clock Cycles Required Clock Address1,3 Cycles A7-A0 20 12 12 12 12 D7-D0 20 A7-A0 11XX XXXX 00XX XXXX A7-A0 10XX XXXX 01XX XXXX D15-D0
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A8-A0 A8-A0 1 1XXX XXXX 0 0XXX XXXX A8-A0 1 0XXX XXXX 0 1XXX XXXX
Q7-Q0 D7-D0
Q15-Q0 D15-D0 27 11 11 11 11 27
Note: 1. X = Don't Care bit. 2. Address bit A8 is not decoded by the M93C56. 3. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction Set for the M93C76 and M93C86
x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data x16 Origination (ORG = 1) Data Required Clock Cycles Required Clock Address1,3 Cycles A9-A0 22 14 14 14 14 D7-D0 22 A9-A0 11 XXXX XXXX 00 XXXX XXXX A9-A0 10 XXXX XXXX 01 XXXX XXXX D15-D0
READ WRITE EWEN EWDS ERASE ERAL WRAL
Read Data from Memory Write Data to Memory Erase/Write Enable Erase/Write Disable Erase Byte or Word Erase All Memory Write All Memory with same Data
1 1 1 1 1 1 1
10 01 00 00 11 00 00
A10-A0 A10-A0 11X XXXX XXXX 00X XXXX XXXX A10-A0 10X XXXX XXXX 01X XXXX XXXX
Q7-Q0 D7-D0
Q15-Q0 D15-D0 29 13 13 13 13 29
Note: 1. X = Don't Care bit. 2. Address bit A10 is not decoded by the M93C76. 3. Address bit A9 is not decoded by the M93C76.
5/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 5. READ, WRITE, EWEN, EWDS Sequences
READ S
D
1 1 0 An
A0
Q ADDR OP CODE
Qn DATA OUT
Q0
WRITE
S CHECK STATUS D 1 0 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
ERASE WRITE ENABLE
S
ERASE WRITE DISABLE 1 0 0 1 1 Xn X0
S
D
D
1 0 0 0 0 Xn X0
OP CODE
OP CODE
AI00878C
Note: For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6.
Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read.
Erase/Write Enable and Disable The Erase/Write Enable (EWEN) instruction enables the future execution of erase or write instructions, and the Erase/Write Disable (EWDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Erase/Write Enable (EWEN) instruction has been executed, erasing and writing remains enabled until an Erase/ Write Disable (EWDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Erase/Write Disable (EWDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Erase/ Write Enable (EWEN) or Erase/Write Disable (EWDS) instructions.
6/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 6. ERASE, ERAL Sequences
ERASE S CHECK STATUS D 1 1 1 An A0
Q ADDR OP CODE BUSY READY
ERASE ALL
S CHECK STATUS D 1 0 0 1 0 Xn X0
Q ADDR OP CODE
AI00879B
BUSY
READY
Note: For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
Erase The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the Ready/ Busy line, as described on page 7. Write For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be
programmed. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described later in this document. Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction. Erase All The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the Ready/Busy line, as described on page 7.
7/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 7. WRAL Sequence
WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0
Q ADDR OP CODE
AI00880C
DATA IN
BUSY
READY
Note: For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
Write All As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described next.
status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven High, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought Low or until a new start bit is decoded.
READY/BUSY STATUS While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select Input (S) is driven High. (Please note, though, that there is an initial delay, of tSLSH, before this
COMMON I/O OPERATION Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details.
8/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 8. Write Sequence with One Clock Glitch
S
C
D
An START "0" WRITE "1"
An-1 Glitch
An-2 D0
ADDRESS AND DATA ARE SHIFTED BY ONE BIT
AI01395
CLOCK PULSE COUNTER In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Cx6 has an onchip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 4 to Table 6. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 9 Address bits + 8 Data bits
9/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 7. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering PDIP: 10 seconds SO: 20 seconds (max) 1 TSSOP: 20 seconds (max) 1 -0.3 -0.3 -4000 Parameter Min. -65 Max. 150 260 235 235 VCC+0.5 6.5 4000 Unit C C V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Input or Output range (Q = VOH or Hi-Z) Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2
Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
10/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 8. Operating Conditions (M93Cx6)
Symbol VCC TA Ambient Operating Temperature (range 3) -40 125 C Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 4.5 -40 Max. 5.5 85 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 9. Operating Conditions (M93Cx6-W)
Symbol VCC TA Ambient Operating Temperature (range 3) -40 125 C Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
Table 10. Operating Conditions (M93Cx6-R)
Symbol VCC TA Supply Voltage Ambient Operating Temperature (range 6) Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C
11/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 11. AC Measurement Conditions (M93Cx6)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.4 V to 2.4 V 1.0 V and 2.0 V 0.8 V and 2.0 V
ns V V V
Table 12. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Parameter
Min. 100
Max.
Unit pF
50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.3VCC to 0.7VCC
ns V V V
Figure 9. AC Testing Input Output Waveforms
M93CXX 2.4V 2V 1V 0.4V INPUT OUTPUT 2.0V 0.8V
M93CXX-W & M93CXX-R 0.8VCC 0.7VCC 0.3VCC
AI02553
0.2VCC
Table 13. Capacitance
Symbol COUT CIN Parameter Output Capacitance Input Capacitance Test Condition VOUT = 0V VIN = 0V Min Max 5 5 Unit pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 1 MHz.
12/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 14. DC Characteristics (M93Cx6, temperature range 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.3 2 15 0.8 VCC + 1 0.4 A V V V V 2 mA Min. Max. 2.5 2.5 1.5 Unit A A mA
50
A
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W.
Table 15. DC Characteristics (M93Cx6, temperature range 3)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC = 5V 10% VCC = 5V 10% VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 -0.3 2 15 0.8 VCC + 1 0.4 A V V V V 2 mA Min. Max. 2.5 2.5 1.5 Unit A A mA
50
A
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W.
13/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 16. DC Characteristics (M93Cx6-W, temperature range 6)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 VCC = 2.5V, S = VIH, f = 1 MHz, Current Product 1 VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 Input Low Voltage (D, C, S) Input High Voltage (D, C, S) VCC = 5V, IOL = 2.1mA VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V -0.3 0.7 VCC 2 0.2 VCC VCC + 1 0.4 A V V V Min. Max. 2.5 2.5 1.5 Unit A A mA
1
mA
ICC
Supply Current (CMOS Inputs)
2
mA
1
mA
10
A
VIL VIH
Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W.
14/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 17. DC Characteristics (M93Cx6-W, temperature range 3)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Test Condition 1 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz VCC = 2.5V, S = VIH, f = 2 MHz VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC -0.3 0.7 VCC VCC = 5V, IOL = 2.1mA VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A VCC = 5V, IOH = -400A VOH Output High Voltage (Q) VCC = 2.5V, IOH = -100A VCC-0.2 V 2.4 0.2 V V Min. Max. 2.5 2.5 2 1 2 0.2 VCC VCC + 1 0.4 Unit A A mA mA A V V V
ICC1 VIL VIH
Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S)
Note: 1. New product: identified by Process Identification letter W.
Table 18. DC Characteristics (M93Cx6-R)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Test Condition 1 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 2 MHz VCC = 1.8V, S = VIH, f = 1 MHz VCC = 1.8V, S = VSS, C = VSS, ORG = VSS or VCC -0.3 0.8 VCC VCC = 1.8V, IOL = 100A VCC = 1.8V, IOH = -100A VCC-0.2 Min. Max. 2.5 2.5 2 1 0.3 0.2 VCC VCC + 1 0.2 Unit A A mA mA A V V V V
ICC1 VIL VIH VOL VOH
Supply Current (Stand-by) Input Low Voltage (D, C, S) Input High Voltage (D, C, S) Output Low Voltage (Q) Output High Voltage (Q)
Note: 1. This product is under development. For more infomation, please contact your nearest ST sales office.
15/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 19. AC Characteristics (M93Cx6, temperature range 6 or 3)
Test conditions specified in Table 11 and Table 8 Symbol fC tSLCH Alt. fSK Parameter Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time M93C46, M93C56, M93C66 Chip Select Set-up time M93C76, M93C86 Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Min.3 D.C. 250 50 100 250 250 250 100 100 100 0 400 200 400 400 10 Max.3 1 Min.4 D.C. 50 50 50 200 200 200 50 50 50 0 200 100 200 200 5 Max.4 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tSHCH
tCSS
tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW
Note: 1. 2. 3. 4.
tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP
tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W.
16/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 20. AC Characteristics (M93Cx6-W, temperature range 6)
Test conditions specified in Table 12 and Table 9 Symbol fC tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW
Note: 1. 2. 3. 4.
Alt. fSK
Parameter Clock Frequency Chip Select Low to Clock High
Min.3 D.C. 250 100 1000 350 250 100 100 100 0
Max.3 1
Min.4 D.C. 50 50 50 200 200 200 50 50 50
Max.4 2
Unit MHz ns ns ns ns ns ns ns ns ns
tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP
Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time
400 200 400 400 10
200 100 200 200 5
ns ns ns ns ms
tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W.
17/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 21. AC Characteristics (M93Cx6-W, temperature range 3)
Test conditions specified in Table 12 and Table 9 Symbol fC tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min.3 D.C. 50 50 50 200 200 200 50 50 50 200 100 200 200 5 Max.3 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. New product: identified by Process Identification letter W.
18/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 22. AC Characteristics (M93Cx6-R)
Test conditions specified in Table 12 and Table 10 Symbol fC tSLCH tSHCH tSLSH2 tCHCL1 tCLCH1 tDVCH tCHDX tCLSH tCLSL tSHQV tSLQZ tCHQL tCHQV tW tCSS tCS tSKH tSKL tDIS tDIH tSKS tCSH tSV tDF tPD0 tPD1 tWP Alt. fSK Clock Frequency Chip Select Low to Clock High Chip Select Set-up Time Chip Select Low to Chip Select High Clock High Time Clock Low Time Data In Set-up Time Data In Hold Time Clock Set-up Time (relative to S) Chip Select Hold Time Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Delay to Output Low Delay to Output Valid Erase/Write Cycle time Parameter Min.3 D.C. 250 50 250 250 250 100 100 100 0 400 200 400 400 10 Max.3 1 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. This product is under development. For more infomation, please contact your nearest ST sales office.
19/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 10. Synchronous Timing (Start and Op-Code Input)
tCLSH C tSHCH S tDVCH D START OP CODE OP CODE tCHDX tCLCH tCHCL
START
OP CODE INPUT
AI01428
Figure 11. Synchronous Timing (Read or Write)
C tCLSL S tDVCH D An tCHQL Q15/Q7 tCHDX A0 tSLQZ Q0 tCHQV tSLSH
Hi-Z Q
ADDRESS INPUT
DATA OUTPUT
AI00820C
Figure 12. Synchronous Timing (Read or Write)
tSLCH C tCLSL S tDVCH D An tCHDX A0/D0 tSHQV Hi-Z Q BUSY tW ADDRESS/DATA INPUT WRITE CYCLE
AI01429
tSLSH
tSLQZ READY
20/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
PACKAGE MECHANICAL PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
b2 A2 A1 b e A L
E
c eA eB
D
8
E1
1 PDIP-B
Notes: 1. Drawing is not to scale.
PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm Symb. Typ. A A1 A2 b b2 c D E E1 e eA eB L 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 - - 4.95 0.56 1.78 0.36 10.16 8.26 7.11 - - 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 - - 0.195 0.022 0.070 0.014 0.400 0.325 0.280 - - 0.430 0.150 Typ. Min. Max. 0.210 inches
21/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
22/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Notes: 1. Drawing is not to scale.
TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c D E E1 e CP L L1 0.550 0.950 0 6 0.400 3.000 4.900 3.000 0.650 0.850 0.050 0.750 0.250 0.130 2.900 4.650 2.900 - Min. Max. 1.100 0.150 0.950 0.400 0.230 3.100 5.150 3.100 - 0.100 0.700 0.0217 0.0374 0 6 0.0157 0.1181 0.1929 0.1181 0.0256 0.0335 0.0020 0.0295 0.0098 0.0051 0.1142 0.1831 0.1142 - Typ. Min. Max. 0.0433 0.0059 0.0374 0.0157 0.0091 0.1220 0.2028 0.1220 - 0.0039 0.0276 inches
23/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Notes: 1. Drawing is not to scale.
TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
24/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
PART NUMBERING Table 23. Ordering Information Scheme
Example: Device Type M93 = MICROWIRE serial access EEPROM Device Function 86 = 16 Kbit (2048 x 8) 76 = 8 Kbit (1024 x 8) 66 = 4 Kbit (512 x 8) 56 = 2 Kbit (256 x 8) 46 = 1 Kbit (128 x 8) 062 = 256 bit (32 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) DS3 = TSSOP8 (3x3mm body size) Temperature Range 6 = -40 to 85 C 31 = -40 to 125 C Option T = Tape & Reel Packing
Note: 1. Produced with High Reliability Certified Flow (HRCF). 2. M93C06 is "Not for New Design". 3. Available only on new products: identified by the Process Identification letter W.
M93C86
-
W MN
6
T
Devices are shipped from the factory with the memory content set at all 1s (FFFFh for x16, FFh for x8).
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
Table 24. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products1 M93C46W6 AYWWF (or AYWWM) Markings on New Products1 M93C46W6 AYWWW
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).
25/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
REVISION HISTORY Table 25. Document Revision History
Date Rev. Description of Revision Document reformatted, and reworded, using the new template. Temperature range 1 removed. TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added, with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and corresponding parameters adjusted).
04-Feb-2003
2.0
26/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
27/27

▲Up To Search▲

Price & Availability of M93C06-R

	To Download M93C06-R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .